If you making these sort of claims, I hope you have something to back it up, at least try to post something with substance. I havent seen any evidence of recent Intel chips failing in batches whilst running at spec. Running chips out of spec can of course cause problems ...
I have never said that Intel chips are failing in mass numbers, but after playing with a few of 13th gen and 14th gen Intel chips I got a good idea of what these chips can comfortably handle, and what settings are pushing these chips hard, potentially damaging them in longer or even shorter periods of time.
I do not think that Intel is enforcing specs well enough, and it does not matter much, if the specs themselves are pushed to the edge.
You can see in the above screenshot from the Korean site, that even a small numbers of failing chips can cause problems to customers and vendors, because even customers with at the moment fully functional chips want to get rid of them, when they lost confidence that they can run reliably.
BTW even when we talk about a special variant of the CPU - fully unlocked and user configurable K model - such special CPU should be in no way less reliable, while running in specs, than the normal CPUs.
It is really painful to see, what Intel does to their own products. For example 14900K limited to 180W power draw runs under an air cooler with the worst Cinebench load really cool - after few minutes the absolute maximum temperature over all cores was 73°C (average temperature much lower, P cores running at 4900 MHz), I just tested it quickly this morning before I left to work.
When you also run limited frequency (lower than specs), you never see even that temperature, when I loaded the P cores with heavy load and let them run at 5200 Mhz, their max temp was lower than what I mentioned.
I would like to
know the comparison of actual electric currents running in the silicon in the two variants of 14900K - my 14900K limited to 5200/4200 MHz and 180W and a stock 14900K placed in the motherboard that does not even enforce the Intel specs power limits. The
strain each silicon chip endures in these two scenarios should be somehow quantifiable.
It should be also noted that temperature sensors are not everywhere in the silicon and the differences in
REAL MAXIMAL temperatures reached in the chips could be dramatically between the above mentioned settings.
I just learned, that according to Blacks equation for electromigration doubling current density can mean reducing mean time to failure up to a fourth, with higher temperature making it even worse.
EDIT:
I tried to calculate Blacks equation for the activation energy 0,9 eV, current density exponent 1,2, doubling current density and increasing temperature from 60°C (333K) to 100°C (373K), and I got
66 times shorter time before failure. Did I make a mistake in the calculation? It seems wrong.
