Thursday, May 2nd 2024

Intel Prepares Core Ultra 9 285K, Core Ultra 7 265K, and Core Ultra 5 245K Arrow Lake-S Desktop CPUs

Hardware leaker Raichu, known for accurately predicting Intel's moves, has unveiled intriguing details about the company's forthcoming desktop CPU lineup. According to the leaks, Intel is supposed to introduce a big shift in its desktop CPU naming convention with the arrival of the Core Ultra 200 series, codenamed Arrow Lake-S. This next-generation lineup promises to deliver one of the most significant performance leaps for desktop processors in recent years, marking a substantial departure from Intel's current naming strategy—a change that hasn't been witnessed in over a decade. The Core Ultra 200 series is expected to encompass a diverse range of tiers and variants, catering to various user needs. This includes the overclockable K models for enthusiasts, F variants without integrated graphics, and potentially low-power T models for energy-efficient SKUs. According to Raichu's leaks, the unlocked K-Series models are rumored to include the high-end Core Ultra 9 285K, the mid-range Core Ultra 7 265K, and the budget-friendly Core Ultra 5 245K. While the absence of a 290K part has raised eyebrows, these names resemble Intel's mobile CPU naming conventions.

To enjoy the Core Ultra 200 series, users will need to upgrade to new motherboards featuring the 800-series chipsets and the LGA-1851 socket. Unlike the Core Ultra 200V Lunar Lake models for mobile devices, details about the desktop version have remained scarce, shrouding the impending launch in an air of mystery. While Raichu's leaks carry significant weight, it's essential to approach such information cautiously. There's a possibility that SKUs like the 290K may still be introduced, as a new KS version, aligning with Intel's traditional naming conventions. The Core Ultra 200 series promises to cater to a wide range of desktop users, from the performance-hungry enthusiasts eyeing the Core Ultra 9 285K to budget-conscious consumers seeking the value proposition of the Core Ultra 5 245K. The Core Ultra 7 265K is expected to strike a balance between performance and affordability, targeting the mid-range segment. As more leaks and official information surface, we will continue to provide updates on this release from Intel.
Source: via VideoCardz
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67 Comments on Intel Prepares Core Ultra 9 285K, Core Ultra 7 265K, and Core Ultra 5 245K Arrow Lake-S Desktop CPUs

#26
dgianstefani
TPU Proofreader
RGAFLSo in that example still, for example in the server and datacentre space, Intel uses more cores, more power with higher clock speeds and still loses in the majority of benchmarks.
Ah, so now you're comparing Golden Cove cores vs Zen 4?
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#27
RGAFL
dgianstefaniAh, so now you're comparing Golden Cove cores vs Zen 4?
What should I compare Zen 4 to then? Let me know and i'll take a look.
Posted on Reply
#28
kondamin
Changes Chip naming scheme, keeps chipset scheme...
Posted on Reply
#29
dgianstefani
TPU Proofreader
RGAFLWhat should I compare Zen 4 to then? Let me know and i'll take a look.
Raptor Cove cores as in the consumer and Xeon lineup for current gen CPUs (Zen 4). Like the original comment you replied to.

Instead of shifting goalposts.
Posted on Reply
#30
SL2
TumbleGeorge10850K
I thought I could predict someones nitpicking, but I failed. :rolleyes:
My post wasn't an attempt to list more than one CPU from each generation.
kondaminChanges Chip naming scheme, keeps chipset scheme...
Oh you think that's a new one? :roll:
Posted on Reply
#31
64K
phintsThis new naming is so baffling and stupid
Well, it's important to keep the average consumer confused about what they are actually getting for their $$$
If it says Ultra in the name then it must be top of the line stuff. :p
Posted on Reply
#32
P4-630
64KWell, it's important to keep the average consumer confused about what they are actually getting for their $$$
If it says Ultra in the name then it must be top of the line stuff. :p
At least they still use "K", so you know it's an unlocked one..

AMD's mobile CPU name scheme isn't much better either though, maybe they'll try that for desktop CPU's next.
Posted on Reply
#33
pressing on
kondaminChanges Chip naming scheme, keeps chipset scheme...
Both got three numbers...
Posted on Reply
#34
dgianstefani
TPU Proofreader
P4-630At least they still use "K", so you know it's an unlocked one..

AMD's mobile CPU name scheme isn't much better either though, maybe the'll try that for desktop CPU's next.
I suspect the "KS" may be replaced by the x90 SKU.

I.e. 290K/KS

That or a mid cycle refresh.

If Intel can keep the naming lined up with the architecture generation, that would be good.

One thing I don't like is the APUs from AMD taking a "generation" number like the 8xxx parts. Or 13/14th gen being the same architecture.

If the first number always refers to the core architecture, would be ideal.
Posted on Reply
#35
Tek-Check
AssimilatorIntel is very obviously using this rebranding to try to shake off the stigma of the turds it's been plopping out for the last god knows how many generations, but they really should've waited until Lunar/Panther Lake to do that.
Are we 100% sure that compute tile is on Intel node?
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#36
Konceptz
eh, both sides have gotten ridiculous with the naming. I'm only interested in how the removal of hyper threading is going to work out.
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#37
Abaidor
I am interested to see when they are going to drop that ridiculous limitation with PCI-E lanes and stop being so stingy. I am on a X299 platform (no gaming) and although I don't need a gazillion lanes, a few more would not hurt on the desktop.
Posted on Reply
#38
dgianstefani
TPU Proofreader
AbaidorI am interested to see when they are going to drop that ridiculous limitation with PCI-E lanes and stop being so stingy. I am on a X299 platform (no gaming) and although I don't need a gazillion lanes, a few more would not hurt on the desktop.
X299 is HEDT. You are comparing to a consumer tier platform.

Bear in mind gen 4/5 lanes are 2 to 4x faster than your gen 3 lanes.
Posted on Reply
#39
P4-630
RogueSixArrow Lake = Intel 20A
Which would be called 2nm by conventional naming standards according to most websites about Arrow Lake.
Posted on Reply
#40
Denver
Even if Intel offers significant improvements in IPC, wouldn't this advantage be mitigated, at least to some extent, by the decrease in clockrate (inherent to the process change)?

Perhaps this could be the reason for discontinuing Hyper-Threading;
Posted on Reply
#41
Tek-Check
There's a bombshell new article over at wccf about the instability rate of hundreds of CPUs tested.

Let's hope Intel can deliver Arrow Lake ASAP, so that the current story goes away.
Posted on Reply
#42
Sabotaged_Enigma
K-series live on? 13th and 14th Gen currently has been un-unlocked already lol
Better cancel all K-series so settle all problems and stop blaming others.
Posted on Reply
#43
RGAFL
dgianstefaniRaptor Cove cores as in the consumer and Xeon lineup for current gen CPUs (Zen 4). Like the original comment you replied to.

Instead of shifting goalposts.
So using the Epyc 9554 64 core processor as Intel only goes up to 64 cores in these benchmarks at Intel Xeon Platinum 8592+ "Emerald Rapids" Linux Benchmarks Review - Phoronix it seems the Epyc wins the majority of the benchmarks, in power it's a bloodbath and it's only in the new AMX instructions there is a decent Intel lead and even there the Epyc wins a few. What goalpost am I shifting?
Posted on Reply
#44
Assimilator
dgianstefaniBear in mind gen 4/5 lanes are 2 to 4x faster than your gen 3 lanes.
Lane speed is irrelevant past PCIe 4.0, we don't need 1 PCIe 5.0 lane, we need 2 PCIe 4.0 lanes. Or rather, we don't need 16 PCIe 5.0 lanes, we need 32 lanes of 4.0. This anti-consumer "HEDT" bullshit needs to end.
Posted on Reply
#45
dgianstefani
TPU Proofreader
AssimilatorLane speed is irrelevant past PCIe 4.0, we don't need 1 PCIe 5.0 lane, we need 2 PCIe 4.0 lanes. Or rather, we don't need 16 PCIe 5.0 lanes, we need 32 lanes of 4.0. This anti-consumer "HEDT" bullshit needs to end.
I understand the sentiment, except more lanes means more silicon and more power draw. So it's not as simple as just adding more. There's a reason AMD went the convoluted route of twin chipsets for AM5 E series boards, which have their own downsides.

The reality is that for 90%+ of people, 16/8 lanes for GPU and 8/16 lanes for M.2 or other things is enough. Just like dual channel RAM is enough.

I'd give as an example the RTX 4090 which lost 2% of performance moving from Gen 4 x16 to Gen 4 x8 in TPU testing.
Posted on Reply
#46
N/A
RogueSixI'm not expecting all that much from Arrow Lake though. Intel keeps emphasizing 18A as the node that is supposed to enable them to return to former glory. They are barely ever even mentioning 20A and if they do then they state that it is a transitional node on the way to 18A. Going by Intel's marketing, this will be the most forgettable node ever and Arrow Lake will be a rather insignificant stepping stone on the way to 18A.
18A is a stepping stone to 16A. and that is a stepping stone to 14A. it's a +, those are the former pluses providing only 10% performance per watt. Unfortunately only post-18A nodes will be on the high NA machines. so everything until then is pretty much skippable. and hopefully for all the tiles.
Posted on Reply
#47
RGAFL
N/A18A is a stepping stone to 16A. and that is a stepping stone to 14A. it's a +, those are the former pluses and nobody cares about a plus providing only 10% performance per watt. Unfortunately only post-18A nodes will be on the high NA machines. so everything until then is pretty much skippable. and hopefully for all the tiles.
Exactly, theses are not whole node jumps but revisions on 2nm. We've reached the point of diminishing returns with Silicon. Whoever finds the next material to take over is going to be a very rich person (if they patent it of course),
Posted on Reply
#49
Wirko
dgianstefaniBear in mind gen 4/5 lanes are 2 to 4x faster than your gen 3 lanes.
That's great but CPUs also need better lane-splitting abilities. And I think we're going to see that in new chips, ARL or whichever is next for the desktop. Why? Because it's pretty much necessary and it costs little to implement. Also because a PCIe 5.0 x2 SSD exists, which (in that mode of operation) only makes sense if it can connect to a 5.0 x2 link on the CPU.
Posted on Reply
#50
dgianstefani
TPU Proofreader
WirkoThat's great but CPUs also need better lane-splitting abilities. And I think we're going to see that in new chips, ARL or whichever is next for the desktop. Why? Because it's pretty much necessary and it costs little to implement. Also because a PCIe 5.0 x2 SSD exists, which (in that mode of operation) only makes sense if it can connect to a 5.0 x2 link on the CPU.
I'm not 100%, but I think it's actually the motherboard that splits lanes.
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